Microprocessor-accessible memory devices have traditionally been classified as either non-volatile or volatile memory devices. Non-volatile memory devices are capable of retaining stored information even when power to the memory device is turned off. Traditionally, however, non-volatile memory devices occupy a large amount of space and consume large quantities of power, making these devices unsuitable for use in portable devices or as substitutes for frequently-accessed volatile memory devices. On the other hand, volatile memory devices tend to provide greater storage capability and programming options than non-volatile memory devices. Volatile memory devices also generally consume less power than non-volatile devices. However, volatile memory devices require a continuous power supply in order to retain stored memory content.
Research and development of commercially viable memory devices that are randomly accessed, have relatively low power consumption, and are non-volatile is ongoing. One ongoing area of research is in resistive memory cells where resistance states can be programmably changed. One avenue of research relates to devices that store data in memory cells by structurally or chemically changing a physical property of the memory cells in response to applied programming voltages, which in turn change cell resistance. Examples of variable resistance memory devices being investigated include memories using variable resistance polymers, perovskite, doped amorphous silicon, phase-changing, glasses, and doped chalcogenide glass, among others.
FIG. 1 shows a basic composition of a typical resistive memory cell such as a phase change memory cell 10 constructed over a substrate 12, having a variable resistance material, e.g., a phase change material 16 formed between a bottom electrode 14 and a top electrode 18. One type of variable resistance material may be amorphous silicon doped with V, Co, Ni, Pd, Fe and Mn as disclosed in U.S. Pat. No. 5,541,869 to Rose et al. Another type of variable resistance material may include perovskite materials such as Pr(1-x)CaxMnO3 (PCMO), La(1-x)CaxMnO3 (LCMO), LaSrMnO3 (LSMO), GdBaCoxOy (GBCO) as disclosed in U.S. Pat. No. 6,473,332 to Ignatiev et al. Still another type of variable resistance material may be a doped chalcogenide glass of the formula AxBy, where “B” is selected from among S, Se and Te and mixtures thereof, and where “A” includes at least one element from Group III-A (B, Al, Ga, In, Tl), Group IV-A (C, Si, Ge, Sn, Pb), Group V-A (N, P, As, Sb, Bi), or Group VII-A (F, Cl, Br, I, At) of the periodic table, and with the dopant being selected from among the noble metals and transition metals, including Ag, Au, Pt, Cu, Cd, Ir, Ru, Co, Cr, Mn or Ni, as disclosed in U.S. Pat. Nos. 6,881,623 and 6,888,155 to Campbell et al. and Campbell, respectively. Yet another type of variable resistance material includes a carbon-polymer film comprising carbon black particulates or graphite, for example, mixed into a plastic polymer, such as that disclosed in U.S. Pat. No. 6,072,716 to Jacobson et al. The material used to form the electrodes 14, 18 can be selected from a variety of conductive materials, such as tungsten, nickel, tantalum, titanium, titanium nitride, aluminum, platinum, or silver, among others.
Much research has focused on memory devices using memory elements composed of chalcogenides. Chalcogenides are alloys of Group VI elements of the periodic table, such as Te or Se. A specific chalcogenide currently used in rewriteable compact discs (“CD-RWs”) is Ge2Sb2Te5. In addition to having valuable optical properties that are utilized in CD-RW discs, Ge2Sb2Te5 also has desirable physical properties as a variable resistance material. Various combinations of Ge, Sb and Te may be used as variable resistance materials and which are herein collectively referred to as GST materials. Specifically, GSTs can change structural phases between an amorphous phase and two crystalline phases. The resistance of the amorphous phase (“a-GST”) and the resistances of the cubic and hexagonal crystalline phases (“c-GST” and “h-GST,” respectively) can differ significantly. The resistance of amorphous GST is greater than the resistances of either cubic GST or hexagonal GST, whose resistances are similar to each other. Thus, in comparing the resistances of the various phases of GST, GST may be considered a two-state material (amorphous GST and crystalline GST), with each state having a different resistance that can be equated with a corresponding binary state. A variable resistance material such as GST whose resistance changes according to its material phase is referred to as a phase change material.
The transition from one GST phase to another occurs in response to temperature changes of the GST material. The temperature changes, i.e., the heating and cooling, can be caused by passing differing amounts of current through the GST material. The GST material is placed in a crystalline state by passing a crystallizing current through the GST material, thus warming the GST material to a temperature which induces a crystalline structure. A stronger melting current is used to melt the GST material for subsequent cooling to an amorphous state. As the typical phase change memory cell uses the crystalline state to represent one logical state binary, e.g., “1,” and the amorphous state to represent another logical state binary, e.g., “0,” the crystallizing current is referred to as a set current ISET (which is sometimes also referred to as a write current) and the melting current is referred to as a reset current IRST (which is sometimes also referred to as an erase current). One skilled in the art will understand, however, that the assignment of GST states to binary values may be switched if desired.
Resistive memory cells 10 are organized into resistive memory bit structures. One method of arranging resistive memory bit structures, as disclosed in U.S. Pat. No. 6,961,258 to Lowrey, is by using a diode accessed cross-point resistive memory array, illustrated in FIG. 2. The memory array 50 includes resistive memory cells 10 electrically interconnected in series with bipolar diodes 60. Bit lines 70a-70e and word lines 80a-80d are connected to external addressing circuitry. The array 50 enables each discrete resistive memory cell 10 to be read from and written to without interfering with the information stored in adjacent or remote memory elements of the array 50. For example, selected resistive memory cell 90 is selected by properly biasing bit line 70b and word line 80b. For a reset operation, bit line 70b may be biased at a pumped voltage VCCP while word line 80b may be kept at 0 V, thus creating a reset voltage drop across the selected resistive memory cell 90 and associated bipolar diode 60 (with accompanying reset current IRST). The other bit lines 70a, 70c, 70d, 70e not being used for selection are biased at 0 V, while the other word lines 80a, 80c, 80d not being used for selection are biased at VCCP. The resulting reverse bias voltage across most of the bits in the array 50 will have a magnitude of VCCP.
For a write operation (which is sometimes also referred to as a set operation) performed on the selected resistive memory cell 90, bit line 70b may be biased at a write voltage while word line 80b may be kept at 0 V. The unselected bits are reverse biased. In order to minimize leakage currents caused by the reverse bias across the bipolar diodes 60, only the section of the array 50 that is being written is biased for the write operation. The remainder of the array 50 is instead reverse biased at a lower magnitude, generally the bias used for a read operation. The reverse bias for the majority of resistive memory cells during a read operation is about 1.5 V. This means that during a set operation, most bipolar diodes 60 in the array 50 are reverse biased with a magnitude of at least 1.5 V, with some reverse biased at an even greater write voltage (e.g., 3 V). Considering the large number of reverse biased diodes in the array 50, the resulting standby current results in significant power consumption.
The array 50 also has a large write-to-read delay. Due to the difference in voltages on the unselected bit lines during write and read operations, a delay of approximately 1 μs is incurred between a write and a read operation (or vice versa). A delay is also incurred on consecutive writes if they are located in different sections of the array 50.
Methods and structures to reduce standby power consumption and reduce operational delays in a diode accessed cross-point resistive memory array are desired.